that produces good efficiency over the top 10dB of operation using devices of equal periphery.
The 2-Way Doherty
Although well documented in the literature, it is worth spending some time revisiting the simple case of the 2-Way Doherty to help understand the 3-Level configuration.
The standard 2 Way Doherty amplifier works by splitting the amplifier into two equally sized amplifiers of half the size (of a single ended Class AB amp with the same peak power capability). The basic principle is that when the output signal level is low, only the main amplifier is active. With increasing output levels the auxiliary amplifier is progressively introduced up to the point where full power is achieved where both main and auxiliary are contributing equally to deliver full power.
Figure 1: Single Ended Class AB and 2 Way Doherty
The 2 Way circuit is configured with the main amplifier biased in Class AB and the auxiliary amplifier biased in class C. This biasing scheme means that at low input drive levels, the main amplifier conducts and the auxiliary amplifier is off. As input levels are increased, the main amplifier drive level also increases and when the output power is a quarter (-6dB) of the amplifier maximum, the auxiliary amplifier starts to conduct current.
At low signal levels when the auxiliary amplifier is not active, the main amplifier (Assuming RL = 25 Ω) “sees” 100 Ω. This means that it reaches full voltage swing at half power. Full voltage swing means that the main amplifier provides maximum efficiency at half its output power. At this point, the amplifier as a whole is delivering a quarter (-6dB) of its peak power capability with maximum efficiency. This is the first point on our efficiency curve in Figure 4.
As input drive level is increased from the 6dB back off point, so the current contribution into the load from the auxiliary increases. This increased current being injected means that the impedance looking into the load increases. The 50 Ω impedance inverter between the load and the main amplifier ensures that that main amplifier sees a reducing load as the current contribution from the auxiliary increases. So, in this regime, as output power increases, there are two processes taking place. The first is that, due to the load modulation from the auxiliary, the main amplifier is effectively increasing in size, that is, it’s capability to produce power is increasing, but all the time it is running at maximum voltage swing and hence maximum efficiency. The other process that is taking place is that both the main and auxiliary amplifier are contributing to the total output power. As drive level increases, so these processes continue up until the auxiliary is at maximum output power (if devices are equal in size) and the currents into the load from the main and auxiliary are equal. At this point the main and auxiliary amplifiers both see 50 Ω.
The key concept to understand in the operation of the Doherty is load modulation. The explanation given in  provides an excellent description of the principals involved and the key elements are repeated here for clarity.
Figure 2: Load Modulation (Inverter Removed)
Figure 1 represents the simplest possible case where two current sources are feeding into a common load. When I2 = 0, then the impedance Z1 is simply equal to RL. If a current is injected into the load from IA then the impedance Z1 is modified to:
Z_1= (1+I_2/I_1 ) R_(L )
If I1 and I2 are equal, then then Z1 = Z2 = 2RL. With the addition of an impedance inverter as shown in Figure 2, this circuit becomes the 2 Way Doherty. The addition of the inverter causes the impedance seen at the main amplifier, Zm, to reduce when the current from the auxiliary is injected into the common load. When the auxiliary is off then Zm = Z02 /RL
Figure 3: 2 Way Doherty Schematic
The theoretical efficiency curve for a 2 Way Doherty is shown below in Figure 4.
Figure 4: 2 Way Doherty Theoretical Efficiency Curve
The Conventional 3 Level Doherty
The conventional 3-Level Doherty is a direct extension of the 2 Way design and is shown in Figure 5.
Figure 5: Conventional 3 Level Doherty
By adjusting the relative device periphery between the main and auxiliary amplifiers, it is possible to achieve a variety of different positions for the efficiency peaks. The designer can use the equations defined in  to locate the efficiency peaks as required. In this paper, we are concerned with signals with around 10dB of PAR. The relative levels of device periphery to achieve an efficiency peak at -9.5dB, -4.4dB and 0dB for the conventional 3 Level Doherty is 1:2:2 where the first digit is the main amplifier followed by Aux 1 and Aux 2 i.e M:A1:A2.
For this configuration, Z01 is required to be 70.7 Ω, Z02 = 33.3 Ω and RL = 20Ω. At the first efficiency peak the main amplifier will see an impedance of 90 Ω. In order to match the output to 50 an impedance inverter of value √20.50 = 31.6 Ω is required.
In essence, the conventional 3 Level Doherty behaves as a 2 Way Doherty up to the second peak (-4.4dB) in efficiency and then from the second peak to full power the main and auxiliary 1 amplifiers are behaving like a main amplifier which is being load modulated by the current contribution from auxiliary 3.
However, there are two main drawbacks of the conventional 3 level Doherty. The first is that different device sizes are required to provide efficiency peaks in the 10dB back off region, which leads to added complexity. The second is that the load modulation of the main amplifier stops in-between the second and final efficiency peaks. This means that the main amplifier is driven into extreme saturation over the last 6dB of output power .
Modified 3 Level Doherty With Equal Sized Devices
The modified 3 Level Doherty design from NXP  achieves similar performance to a conventional 3 Level Doherty but without having to accommodate output transistors of different sizes. Using transistors of equal sizes for the main and auxiliary stages has a number of practical benefits, including the use of a single “unit cell” RF design. The basic amplifier unit cell for the main and auxiliaries can be of the same (or very similar) design which reduces development time. Also, having three of the same parts rather than two different parts on the bill of materials leads to economies of scale, which is important for what are likely to be the most expensive components in the amplifier. The configuration also leads to proper load modulation of the main amplifier whose load impedance, as we shall see, steadily reduces as drive level is increased.
A schematic diagram of the modified 3 level Doherty is shown in Figure 6.
Figure 6: Modified 3 Level Doherty Schematic
The best way to understand the operation is to start at low signal levels and progressively increase the input drive level and discuss the operation at each efficiency peak and refer to the efficiency curve in Figure 7.
Figure 7: Theoretical Efficiency Curve For Modified 3 Level Doherty
Each amplifier depicted as a triangle in Figure 6 is termed a “unit cell”. Each unit cell in this example delivers maximum output power when driving a 50 Ω load. The unit cell also contains phase offset lines to ensure that the electrical length of an auxiliary (and main) stage is 180 degrees from the active device to the point at which the amplifier is connected into the Doherty combiner circuit. This ensures that when the auxiliary amplifier is switched off an open circuit is presented to the Doherty combiner and the minimum power is dissipated in the auxiliary output matching circuits. The main amplifier is biased in a class AB mode, Auxiliary 1 is biased at around 0.7V and Auxiliary 2 is biased at around 0V when using enhancement mode LDMOS transistors. These values provide the required progressive switching of the Auxiliary amplifiers. Note, that the load value is 16.66Ω in this example, this is transformed up to 50Ω with a 28.8Ω quarter wave inverter.
At low signal levels, in the regime before point A is reached, only the main amplifier is active. The impedance presented to the main amplifier unit cell at this point is 150 Ω.
At point A the conditions seen in Table 1 apply. :
Table 1: First Efficiency Peak Parameters
As the input drive level increases, so we move to the region in between point A and B in Figure 7. At point A, Auxiliary 1 switches on and starts to deliver current into the common output load RL. This increase in current in the common load causes the impedance seen from the main amplifier at Node A to increase. The action of the inverter Z01, in the main path, causes the impedance seen by the main amplifier to fall. This reduction in output impedance results in the main amplifier being able to deliver more power into the common load whilst remaining in voltage saturation.
As drive level is increased, so this process continues until the current in the load due to the auxiliary is half that of the current in the load due to the main and the following condition is reached:
This condition is point B in Figure 7 and is our second efficiency peak. At this point, applying Equation 1, the impedance seen from the main amplifier looking into Node A is given by :
Z_(M_NodeA )= R_L (1+I_A1/I_M )= 3/2 R_L=25Ω
So, the impedance seen by the main device looking into 50Ω inverter Z01¬ is 100Ω.
Also, the impedance seen from the Auxiliary branch looking into Node A is given by:
Z_(A_NodeA )= R_L (1+I_M/I_A1 )= 〖3R〗_L=50Ω
The impedance at node B looking from Auxiliary2 is therefore 12.5Ω(due to Z03) and the impedance seen by Auxiliary 1 unit cell amplifier is 200Ω Since the main amplifier and auxiliary 1 are both running at voltage saturation, they both deliver maximum efficiency, hence the peak in efficiency. The parameters for the amplifier at this second efficiency peak are given in table 2.
Table 2: Second Efficiency Peak Parameters
The bias of Auxiliary 2 is set such that it starts to turn on and deliver current into the output load when Equation 2 is satisfied. The increase in current further reduces the main impedance and allows it to deliver more power. The increased current into the load also reduces the load impedance seen by Auxiliary 1 so this device delivers more power and further increases load current. This increase in current continues until the contribution from each amplifier is equal and the following is satisfied:
The two auxiliaries deliver a total normalized current of 2 into the load and the main delivers 1. This is point C in Figure 7. At this point, the impedance from the main branch looking into Node A is now
Z_(M_NodeA )= R_L (1+I_(A1+IA2)/I_M )= 〖3R〗_L=50Ω
So the main amplifier sees 50 and delivers full power. The impedance seen from the auxiliary branch looking into Node A is given by
Z_(A_NodeA )= R_L (1+I_M/(I_A1+I_A2 ))= 3/2 R_L=25Ω
Since Z03 is a 25Ω inverter, so the impedance looking into Node B is also 25. This is the correct impedance for two 50 loads in parallel. The parameters for the amplifier at this third and final efficiency peak are given below in table 3.
Table 3: Third Efficiency Peak Parameters
As well as the design of the output network, there are a number of practical design considerations of this type of amplifier that need to be considered. The first is that the gain of the 3 Level amplifier is inherently quite low because of the 3 way input split. This results in the small signal gain being a minimum of 4.7dB lower than that obtained from a single ended device. This is less of an issue at lower cellular bands, but can become a problem at higher frequencies where gain is at a premium. The quarter wave transformers used extensively in this design, limit the bandwidth to around 4 to 5% maximum, so is only currently applicable to narrow band applications
A 2.14 GHz 3 Level Doherty
In order to demonstrate the concept a 2.14 GHz version of the NXP 3 Level amplifier was designed and manufactured. A photograph of the amplifier is shown below in Figure 8.
Figure 8: 2.14GHz 3 Level Doherty
The 3 way input splitting (-4.7dB) is achieved by using a 5dB directional coupler cascaded with a 3dB hybrid coupler. The transistors used are twin LDMOS devices running from 28V (normally used for push pull or balanced applications) with one of the transistors not used in the upper device. The output power of this amplifier cannot be published here, so the results are presented as back off levels from full output power, which in this case is classed as around 2dB output compression. As can be seen, the design objective of 40% drain efficiency at 10dB back off has been achieved over the band of interest. Although not shown here, the small signal gain of this amplifier was around 16dB with a power gain at full power of 14dB.
Figure 9: Experimental Results For a 2.14GHz 3 Level Doherty Amplifier
The 3 Level Doherty in Summary
An overview and explanation of the operating principle of the Modified 3 Level Doherty form NXP has been presented with experimental results of a fabricated amplifier shown.
References RF Power Amplifiers for Wireless Communications – Steve C. Cripps, Artech House, 1999 A Mixed-Signal Approach Towards Linear and Efficient N-Way Doherty Amplifiers W. C. Edmund Neo et al, IEEE-MTT VOL. 55, NO. 5, MAY 2007 3 Way Doherty Amplifier With Minimum Output Network, US Patent US20100315162, NXP
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